Meeting future system performance needs requires input/output (I/O) bandwidth that can scale with processing and application demands. Alongside these increasing performance demands, the enterprise server and communication markets require improved reliability, security and quality of service guarantees. Fortunately, technology advances and high speed point-to-point interconnects are enabling system designers to break away from the bandwidth limitations of multiple drop, parallel buses. To this end, system designers have discovered a high-performance, third generation I/O (3GIO) interconnect that will serve as a general purpose I/O interconnect for a wide variety of future computing and communications platforms.
3GIO comprehends the many I/O requirements presented across the spectrum of computing and communications platforms and rolls them into a common scalable and extensible I/O industry specification. One implementation of 3GIO is the PCI Express specification. The PCI Express basic physical layer includes a differential transmit pair and a differential receiver pair. As such, dual simplex data on these point-to-point connection referred to herein as a “point-to-point link,” is self-clocked and its bandwidth increases linearly with interconnect (link) width and frequency. In addition, PCI Express also provides a message space within its bus protocol that is used to implement legacy side band signals. As a result, a further reduction of signal pins produces a very low pin count connection for components and adapters.
PCI Express (PCIe) provides backward compatibility for conventional PCI, which is based on a multi-drop parallel bus implementation. To provide backward compatibility with conventional PCI, PCIe retains the device concept of conventional PCI. As described herein, the device concept of conventional PCI requires that a device provide a one-to-one correspondence with a piece of silicon or I/O card that plugs into a slot of a computer system. Hence, PCIe retains the device concept of conventional PCI, which requires a one-to-one correspondence between devices and I/O cards, thereby limiting an I/O card to include a single internal device. Unfortunately, this limitation can create a nuisance for non-legacy software, which may be able to handle a single card, which implements multiple logical devices.